发明名称 |
TRANSISTOR WITH ASYMMETRY FOR DATA STORAGE CIRCUITRY |
摘要 |
A transistor (22) having a source (30) with higher resistance than its drain (40) is optimal as a pull-up device (20) in a storage circuit (10). The transistor has a source region having a source implant having a source resistance. The source region is not salicided. A control electrode region (50) is adjacent the source region for controlling electrical conduction of the transistor. A drain region (40) is adjacent the control electrode region and opposite the source region. The drain region has a drain implant that is salicided and has a drain resistance. The source resistance is more than the drain resistance because the source region having a physical property that differs from the drain region. |
申请公布号 |
KR20090036570(A) |
申请公布日期 |
2009.04.14 |
申请号 |
KR20097001710 |
申请日期 |
2007.05.03 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
WHITE TED R.;BURNETT JAMES D.;WINSTEAD BRIAN A. |
分类号 |
H01L21/8244;H01L21/336;H01L27/11 |
主分类号 |
H01L21/8244 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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