发明名称 |
Method of generating an enable signal of a standard memory core and relative memory device |
摘要 |
A memory device is configured for communicating with one of two different serial protocols, respectively an LPC or an SPI protocol, as well as with a parallel communication protocol through a multi-protocol interface while requiring only a single additional pin as compared to a standard memory device accessible with a parallel communication protocol. This result is achieved by exploiting the same pin for providing a timing signal for serial mode communications or an address multiplexing signal for parallel mode communications. The additional pin is used for conveying a start signal of an A/AMUX parallel communication protocol. The interface includes logic circuits that generate an enable signal for the standard memory core of the memory device.
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申请公布号 |
US7519751(B2) |
申请公布日期 |
2009.04.14 |
申请号 |
US20040886003 |
申请日期 |
2004.07.07 |
申请人 |
PERRONI MAURIZIO FRANCESCO;POLIZZI SALVATORE;SCAVUZZO ANDREA |
发明人 |
PERRONI MAURIZIO FRANCESCO;POLIZZI SALVATORE;SCAVUZZO ANDREA |
分类号 |
G06F13/00;G06F13/42 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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