| 摘要 |
Disclosed is a frequency multiply circuit for outputting an output signal obtained by variably multiplying the frequency of an input signal includes a synchronous delay circuit, a multiplexing circuit, and a control circuit. The synchronous delay circuit includes a period measuring delay circuit for measuring the period of the input signal and delay reproducing delay circuits each with a delay time thereof variably set based on the period measured by the period measuring delay circuit, for respectively reproducing the delay time. The multiplexing circuit receives a plurality of signals of different phases output from the synchronous delay circuits, for multiplexing. The control circuit variably sets the number of the delay stages of the period measuring delay circuit and the numbers of the stages of the delay reproducing delay circuits, according to the set frequency-multiplication factor. The output signal synchronized with the input signal and obtained by multiplying the frequency of the input signal is output from the multiplexing circuit.
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