| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of preventing the occurrence of a frequency shift upon occurrence of changes in the level of an input to an analog/digital (A/D) converter, by preventing phase-locked loop (PLL) control from not operating properly. <P>SOLUTION: The frequency synthesizer includes a carrier remove 16, an inverse rotational vector multiplier 17, a phase time difference detector 18, an adder 19, a phase difference accumulator 20, a loop filter 21, a parameter output part 25, an amplitude information detector 26, a filter 27, and a multiplier 28 configured by a field programmable gate array (FPGA); unlock detection means monitors a correction value in an AGC circuit, obtained on the basis of the amplitude information detected by the amplitude information detector 26. When the value lies within a proper range, a lock (synchronization) processing is performed under PLL control; whereas when the value is off the proper range, an unlock state in PLL control is detected. <P>COPYRIGHT: (C)2009,JPO&INPIT |
