发明名称 DYNAMIC TIMING ADJUSTMENT IN A CIRCUIT DEVICE
摘要 A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time (502). The method further includes receiving an input signal at an input of a first latch of the circuit device (504) and receiving an output signal at an input of a second latch of the circuit device (506). The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal (508) and delaying the clock signal (510) by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic (508, 510). The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal (512) and latching the output signal at the second latch responsive to the second adjusted clock signal (514).
申请公布号 WO2007120957(A3) 申请公布日期 2009.04.09
申请号 WO2007US61188 申请日期 2007.01.29
申请人 FREESCALE SEMICONDUCTOR INC.;JARRAR, ANIS, M.;MACDONALD, COLIN 发明人 JARRAR, ANIS, M.;MACDONALD, COLIN
分类号 G06F1/12 主分类号 G06F1/12
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