| 摘要 |
<p>A sophisticated high-k metal gate electrode structure may be formed after the deposition of a first part of an interlayer dielectric material (119, 119p, 119n, 119s), thereby providing a high degree of process compatibility with conventional CMOS techniques. Thus, sophisticated strain-inducing mechanisms may be readily implemented in the overall process flow, while nevertheless avoiding any high temperature processes during the formation of the sophisticated high-k dielectric gate stack (11Op, 11On).</p> |
