发明名称 SEMICONDUCTOR MEMORY TEST APPARATUS
摘要 PROBLEM TO BE SOLVED: To improve efficiency of redundancy processing by more speedily obtaining the line fail count after line determination than before, and to reduce a circuit scale on the side of a semiconductor memory test apparatus by dispensing with a line mask with respect to a semiconductor memory. SOLUTION: This apparatus is provided with a line fail counter which counts the numbers of fail cells detected from the semiconductor memory to be tested with respect to each of X-lines and Y-lines; and a line determination flag which is set when a fail cell positioned on a corresponding line can be repaired by assigning an X spare line and a Y spare line to the fail cells. On the basis of a set line determination flag, the fail cell positioned on the corresponding line is detected and the counted value of the line fail counter is subtracted and updated. On the basis of the subtracted and updated counted value of the line fail counter, the X spare line and the Y spare line are assigned in combination with each other to repair the unrepaired fail cells. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009076136(A) 申请公布日期 2009.04.09
申请号 JP20070243619 申请日期 2007.09.20
申请人 YOKOGAWA ELECTRIC CORP 发明人 KOJIMA TETSUJI;KIMURA TAKAHIRO
分类号 G11C29/44 主分类号 G11C29/44
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