发明名称 LOGICAL SIMULATION DEVICE AND LOGICAL SIMULATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a logical simulation device and a logical simulation method for effectively verifying a failure of a logic circuit which is caused under complicated conditions. <P>SOLUTION: This logic simulation device for verifying the logic circuit by determining an input by using random numbers is provided with: a score measurement means for measuring an internal state of the logic circuit during simulation, and for outputting it with scores; a history data storage means for associating the random numbers generated during simulation and the scores output by the score measurement means with time, and for storing it as history data in a prescribed storage region; and a reproduction means for specifying the time with high scores by using the history data, and for determining the input by using the random numbers recorded in the history data, and for performing reproduction until the specified time in the simulation. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009075811(A) 申请公布日期 2009.04.09
申请号 JP20070243474 申请日期 2007.09.20
申请人 FUJITSU MICROELECTRONICS LTD 发明人 TABATA YUSUKE
分类号 G06F17/50;G01R31/28;G06F11/22;G06F11/25 主分类号 G06F17/50
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