| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce unnecessary power consumption and occupied areas, while setting efficiently delay time from signal input to signal output. <P>SOLUTION: A variable delay circuit DWR comprises a plurality of unit circuits 31-1 to 31-10 connected in series, and can increase or decrease the number of unit circuits 31 in which a signal passes, to change delay time from signal input to signal output. The unit circuits 31 is configured to selectively operate at a through operation mode or a feedback operation mode. At the through operation mode, a signal inputted from a pre-stage unit circuit 31 is outputted to a post-stage unit circuit 31, while a signal inputted from the post-stage unit circuit 31 is outputted to the pre-stage unit circuit 31. At the feedback operation mode, a signal inputted from the pre-stage unit circuit 31 is outputted to the pre-stage unit circuit 31, while a signal inputted from the post-stage unit circuit 31 is outputted to the post-stage unit circuit 31. <P>COPYRIGHT: (C)2009,JPO&INPIT |
