发明名称 DESIGN METHOD OF INTEGRATED CIRCUIT DEVICE, DESIGN SUPPORT SYSTEM OF INTEGRATED CIRCUIT DEVICE, DESIGN SUPPORT PROGRAM OF INTEGRATED CIRCUIT DEVICE, MACROCELL, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a design method of an integrated circuit device capable of reducing characteristic variation of a macrocell due to the difference of an automatic generation part of a dummy pattern for a flattening process of an insulation layer surface; and the like. SOLUTION: This design method of an integrated circuit device includes: a step (step S10) of arranging and wiring a macrocell having the dummy pattern for a surface flattening process formed thereon, and including layout information, in at least one wiring layer, based on circuit connection information of the integrated circuit device; a step (step S14) of detecting a region capable of arranging a predetermined dummy pattern for the surface flattening process based on the layout information of the integrated circuit device after the arrangement and wiring; and a step (step S16) of generating a dummy pattern in the region. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009076766(A) 申请公布日期 2009.04.09
申请号 JP20070245744 申请日期 2007.09.21
申请人 SEIKO EPSON CORP 发明人 KUWANO SHUNICHI
分类号 H01L21/82;G06F17/50;H01L21/3205;H01L21/822;H01L23/52;H01L27/04 主分类号 H01L21/82
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