| 摘要 |
PROBLEM TO BE SOLVED: To provide a layout verification program, layout verifying method and layout verification device for preventing a decrease in yield. SOLUTION: A computer 1 has following functions. A verifying means 2 performs timing verification by the number of vias which is less than a plurality of vias 4 and 5 provided in a prescribed wiring part 3 by a layout design. A layout modifying means 6 adjusts the number of vias of the wiring part 3 to modify the layout when a delay time does not satisfy a prescribed time as a result of the timing verification. The occurrence of a timing error can be prevented even when cutting vias or the like, so that yield and reliability can be improved. COPYRIGHT: (C)2009,JPO&INPIT
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