| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock control circuit which stops a clock signal or reduces a frequency before or after a state of a signal with large delay time changes. <P>SOLUTION: The clock control circuit includes: a gate circuit 1 which stops supply of the clock signal; and a gate control circuit 13 which stops the supply of the clock signal by the gate circuit 1 in response to a reset signal, generates an internal reset signal whose logic level changes in response to the reset signal, and stops the supply of the clock signal before and after the logic level of the internal reset signal changes. Consequently, malfunctions of flip-flops 21-25 are prevented. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
