发明名称 POWER SAVING CONTROL DEVICE FOR MULTIPROCESSOR SYSTEM, AND MOBILE TERMINAL
摘要 <p><P>PROBLEM TO BE SOLVED: To effectively reduce power consumption while securing real time performance without assuming that a processor load is set to a low load state according to the lapse of a time in a multiprocessor system in which both performance securing/performance non-securing tasks coexist. <P>SOLUTION: This multiprocessor system equipped with a plurality of processors for performing the distributed processing of a plurality of tasks includes an assignment control means E1 for controlling the assignment of each performance securing task to each processor so that the number of use processors can be minimized on the basis of a relative relationship between each of processing performance valueΦi of each performance securing task Ti and each of processing capability values Wj of a processor Pj in consideration of a real time performance timeτi required by each performance securing task; and an operation state control means E2 for applying a power saving state to the operating states of non-use processors to which the assignment of the performance securing tasks has been canceled as the result of the assignment control means. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2010277300(A) 申请公布日期 2010.12.09
申请号 JP20090128667 申请日期 2009.05.28
申请人 PANASONIC CORP 发明人 ICHINOSE NAOYA;MORITA RYOKO;KOBAYASHI KEITA;NISHIMURA OSAMU
分类号 G06F9/50;G06F1/26;G06F1/32 主分类号 G06F9/50
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