| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reliably transfer data between asynchronous circuits. <P>SOLUTION: From a NAND, DQSs 22 and DQs 21 by the number of transfer data is sequentially output. An I/O block 10 writes transfer data in an FIFO 30 through a data retention circuit 11. The data written in the FIFO 30 are read in synchronization with a clock signal of a data transfer destination, and taken in the transfer destination through a multiplexer 42. Final data is retained in the data retention circuit 11, but not transferred to the FIFO 30. The multiplexer 42 acquires the final data retained in the data retention circuit 11 in synchronization with a system clock using a path directly connected to the data retention circuit 11. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
