| 摘要 |
<p>An output transistor bias generation circuit (A), which applies a bias voltage to one (N1) of two NMOS transistors (N1, N2) which form the output circuit of a stack structure, comprises: diode-connected NMOS transistors (N4, N5) which are inserted between an external connection pad (IO) and the gate of the NMOS transistor (N1), said external connection pad (IO) being connected to an external signal line with a voltage higher than the power supply voltage of the LSI; diode-connected NMOS transistors (N6, N7, N8) which are inserted between the gate of the NMOS transistor (N1) and a ground line; a diode-connected NMOS transistor (N9) which is inserted between the power supply line and the gate of the NMOS transistor (N1); and a capacitance-connected NMOS transistor (N10) which is inserted between the gate of the NMOS transistor (N1) and the ground line.</p> |
