| 摘要 |
PROBLEM TO BE SOLVED: To shorten a design TAT while suppressing the occurrence of design rule error and short-circuiting. SOLUTION: A designing method for a semiconductor integrated circuit includes (A) dividing a layout region where a wiring pattern and a special pattern are arranged into a plurality of divided regions, wherein the special pattern has a larger minimum interval determined by a design rule than the wiring pattern. Further, the designing method includes, in terms of each of the divided regions, the steps of: (B) extracting a special pattern included in a region of predetermined width surrounding each of the divided regions as a peripheral pattern; and (C) determining a dummy pattern arrangement region included in each of the divided regions. Furthermore, the designing method includes the steps of: (D) adding a dummy pattern to a dummy pattern arrangement region of each divided region while avoiding a design rule error with respect to an extracted peripheral pattern at a periphery of each of the divided regions; and (E) coupling a plurality of divided regions to which dummy patterns are added to each other. COPYRIGHT: (C)2011,JPO&INPIT |
