| 摘要 |
A data processing apparatus 200 includes vector processing unit 206, comprising pipeline stages (104, 106, 108) and plural lanes of parallel processing, and has access to vector register data store 208, having a plurality of registers, during execution of a sequence of vector instructions. Skip indication storage (506) maintains a skip indicator for each lane. Vector processing unit 206 responds to a vector skip instruction to update skip indication storage by setting the skip indicator for a determined one or more lanes. Vector processing unit 206 responds to a vector operation instruction to perform an operation, in parallel, on data elements input to the plurality of lanes, but to exclude from the performance of the operation any lane whose associated skip indicator is set. Vector skip instructions may indentify a bit mask for lanes. Skip indicators may be skip counters or remain set until a skip end instruction is executed. Lanes may be excluded by preventing operations or discarding result values. The nesting of vector skip instructions is allowed. Skip indicators may be set by evaluating condition codes. The invention allows vector instructions to be performed conditionally within lanes without any modification to the vector instructions specifying those operations. |
