发明名称 Stacked wafer or die packaging with enhanced thermal and device performance
摘要 <p>An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and the device layer, and a heat spreading and stress engineering region in the substrate and adjacent to the device layer. The via contacts a metal layer in the metallization region.</p>
申请公布号 GB2444467(B) 申请公布日期 2010.12.08
申请号 GB20080006342 申请日期 2006.10.24
申请人 INTEL CORPORATION 发明人 RAJASHREE BASKARAN;SHRIRAM RAMANATHAN;PATRICK MORROW
分类号 H01L23/367;H01L21/768;H01L23/48;H01L25/065 主分类号 H01L23/367
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