METHOD OF TESTING LEAKAGE CURRENT OF BIT-LINE IN NON VOLATILE MEMORY

摘要

PURPOSE: A bit line leak current testing method of nonvolatile memory device is provided to improve the sensing margin of a test operation by precharging a first bit line using high voltage and sensing the voltage of a second bit line using a page buffer. CONSTITUTION: A bit line selection part(110) comprises a plurality of NMOS transistors. A precharging unit(120) comprises a PMOS transistor(PM1) connected between a voltage terminal(VDD) and a sensor node(SO). A cache latch(130) comprises a plurality of NMOS transistors and an inverter. A main latch(140) comprises a plurality of NMOS transistors and an inverter.