发明名称 |
Integrated clock and power distribution |
摘要 |
An integrated clock and power distribution network in a semiconductor device includes assigning a first tile to a location on a placement grid corresponding to a top metal layer. An orientation is assigned to the first tile relative to the top metal layer placement grid. The first tile is placed on a representation corresponding to the top metal layer in accordance with the assignments. A second tile is assigned to a location on a placement grid corresponding to a top-1 metal layer. The orientation is assigned to the second tile relative to the top-1 metal layer placement grid. The second tile is placed on a representation corresponding to the top-1 metal layer in accordance with the assignments. The first and second tile are arranged as a full-dense-mesh distribution structure. The first tile includes an integrated clock and power distribution structure. The second tile includes a low impedance underpass structure. |
申请公布号 |
US7847408(B2) |
申请公布日期 |
2010.12.07 |
申请号 |
US20090355653 |
申请日期 |
2009.01.16 |
申请人 |
ORACLE AMERICA, INC. |
发明人 |
MASLEID ROBERT P.;COLLIER DUNCAN |
分类号 |
H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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