发明名称 Logic circuit including a plurality of master-slave flip-flop circuits
摘要 According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data, a second master latch included in another of the master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data and a slave latch included in one of the master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the second master latch.
申请公布号 US7847582(B2) 申请公布日期 2010.12.07
申请号 US20080155829 申请日期 2008.06.10
申请人 FUJITSU LIMITED 发明人 SATSUKAWA YOSHIHIKO
分类号 H03K19/00 主分类号 H03K19/00
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