| 摘要 |
An output enable signal generating circuit including a first count value generation unit that provides a first count value by executing a counting operation, starting from an initial count value corresponding to a CAS latency information, the counting operation being executed in response to an internal clock signal, a second count value generation unit that provides a second count value that is counted in response to an external clock signal and an output enable signal generation unit for generating an output enable signal that is activated at every timing when the second count value and the first count value become equal to each other, in response to each of a plurality of read commands.
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