| 摘要 |
A semiconductor memory device includes: a delay locked loop (DLL) clock buffer for buffering a system clock in response to the a buffer enable signal; a DLL circuit for generating a delay locked loop (DLL) clock by performing a delay locking operation using the buffered system clock; and a DLL clock buffer controller for generating the buffer enable signal in response to a code signal and a clock enable signal, the code signal containing information about whether to perform the delay locking operation.
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