发明名称 |
Low power, self-gated, pulse triggered clock gating cell |
摘要 |
A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell.
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申请公布号 |
US7808279(B2) |
申请公布日期 |
2010.10.05 |
申请号 |
US20090503059 |
申请日期 |
2009.07.14 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
SRIVASTAVA ANUBHAV;MAHAJAN ABHISHEK;SRIVASTAVA NEHA |
分类号 |
H03K19/00;H03K5/05 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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