发明名称 |
Critical area computation of composite fault mechanisms using Voronoi diagrams |
摘要 |
Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.
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申请公布号 |
US7810060(B2) |
申请公布日期 |
2010.10.05 |
申请号 |
US20080132714 |
申请日期 |
2008.06.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALLEN, JR. ROBERT J.;PAPADOPOULOU EVANTHIA;TAN MERVYN YEE-MIN |
分类号 |
G06F17/50;G01R31/28;G11C29/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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