| 摘要 |
A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.
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