发明名称 MULTISTANDARD VARIABLE LENGTH DECODER WITH HARDWARE ACCELERATOR
摘要 An embodiment includes an apparatus that includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.
申请公布号 KR100985361(B1) 申请公布日期 2010.10.04
申请号 KR20077024958 申请日期 2006.03.30
申请人 发明人
分类号 G06F9/06 主分类号 G06F9/06
代理机构 代理人
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