发明名称 Unit cell compression circuit and method
摘要 A circuit includes a compression sub-circuit having an input and an output for dumping excess current, a voltage bucket, and a current source. The voltage bucket, such as a capacitor, and the current source, such as a photodetector, are coupled in parallel to the input of the compression sub-circuit. Preferably, the compression sub-circuit is a single FET having a gate voltage selected to allow current to bleed off or be dumped through the FET as the capacitor approaches being full, and dumps excess photocurrent when the capacitor is full. The capacitor is nearly full when it is at least three quarters full, and is substantially full or approaching being full when it is at least 90% of capacity. In a photodetector embodiment, one plate of the capacitor is coupled to the FET and the opposed second plate is coupled to a ramping voltage circuit.
申请公布号 US7800672(B1) 申请公布日期 2010.09.21
申请号 US20050125510 申请日期 2005.05.09
申请人 RAYTHEON COMPANY 发明人 GRAHAM ROGER W.;CAULFIELD JOHN T.
分类号 H04N5/335;H04N3/14 主分类号 H04N5/335
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