发明名称 |
Functional block level clock-gating within a graphics processor |
摘要 |
An embodiment of the invention includes receiving an indicator of a flow of data associated with a graphics processing stage within a graphics pipeline of a graphics processor. A clock signal to a portion of the graphics processing stage is modified based on a status of the flow of data. The clock signal is received from a clock signal generator within the graphics processor.
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申请公布号 |
US7802118(B1) |
申请公布日期 |
2010.09.21 |
申请号 |
US20060614248 |
申请日期 |
2006.12.21 |
申请人 |
NVIDIA CORPORATION |
发明人 |
ABDALLA KARIM M.;HASSLEN, III ROBERT J. |
分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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