发明名称 DELAY ELEMENT AND INTEGRATED DELAY ELEMENT
摘要 PROBLEM TO BE SOLVED: To provide a delay element which secures voltage amplitude of an output signal without depending on oscillation frequencies. SOLUTION: This invention relates to the delay element, including a delay circuit 1a and a current source circuit 2a. The delay circuit 2a consists of Nch transistors MN1-8. The Nch transistors MN3 and MN5 are connected to the Nch transistor MN1, and the Nch transistors MN4 and MN7 are connected to the Nch transistor MN2. The Nch transistors MN6 and MN8 are connected to the Nch transistors MN5 and MN7, respectively. The Nch transistors MN3 and 4 are controlled by control voltage VC. A gate of the Nch transistor MN5 is connected to an output node OUTB. A gate of the Nch transistor MN7 is connected to an output node OUT. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010273111(A) 申请公布日期 2010.12.02
申请号 JP20090123189 申请日期 2009.05.21
申请人 RENESAS ELECTRONICS CORP 发明人 HEIKO YASUYUKI
分类号 H03K5/13;H03K3/354 主分类号 H03K5/13
代理机构 代理人
主权项
地址