发明名称 |
SYSTEM AND METHOD FOR OPERATING A PACKET BUFFER |
摘要 |
A technique implements a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of FIFO queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. The high-speed cache portion contains FIFO data that contains head and/or tail associated with the novel FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion.
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申请公布号 |
CA2477668(C) |
申请公布日期 |
2011.01.18 |
申请号 |
CA20032477668 |
申请日期 |
2003.04.28 |
申请人 |
CISCO TECHNOLOGY, INC. |
发明人 |
KEY, KENNETH M.;MAK, KWOK KEN;SUN, XIAOMING |
分类号 |
H04L29/06;H04L12/56;H04L29/08 |
主分类号 |
H04L29/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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