| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of executing efficiently a delay test of a boundary domain. SOLUTION: This circuit includes: an internal circuit part 10 including a plurality of scan flip-flops; an IO pin 20; and a delay test circuit part 202 connected to a data path for transferring an output from the internal circuit part 10 to the IO pin 20, for dividing the data path into an internal circuit part side path and an IO pin side path, and for a delay test for determining a delay time of the data path. The delay test circuit part 202 includes an internal circuit part side scan flip-flop 203 for receiving first test data outputted from the internal circuit part 10 through the internal circuit part side path, and a plurality of IO pin side scan flip-flops 204, 205 for holding second test data to be outputted to the IO pin 20 through the IO pin side path. COPYRIGHT: (C)2011,JPO&INPIT
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