Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions

摘要

A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout of the restricted layout region. The plurality of diffusion region layout shapes include a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. A gate electrode level layout is defined include a number of rectangular-shaped layout features placed to extend in only a first parallel direction, and defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.