| 摘要 |
A memory control circuit includes a clock generation circuit that generates a clock signal and provides the clock signal to an external memory device, and at least one retention circuit that retains a data signal provided from the external memory device only under a significant state of a data strobe signal, which is provided together with the data signal. The memory control circuit controls data acquisition from the retention circuit in accordance with the clock signal. A data acquisition timing judgment unit, by monitoring the clock signal, judges whether or not a timing of the data acquisition has arrived. A data strobe signal correction unit maintains the significant state of the data strobe signal until it is judged that the data acquisition timing has arrived.
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