| 摘要 |
Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.
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