发明名称 DATA PATH CELL ON SeOI SUBSTRATE WITH BURIED BACK CONTROL GATE BENEATH INSULATING LAYER
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device formed on an SeOI (Semiconductor-On-Insulator) substrate on the basis of a fundamental data-path cell. SOLUTION: A data path cell is adapted especially to its environment for use in an integrated circuit produced on a semiconductor-on-insulator substrate comprising a thin layer of semiconductor material separated from a bulk substrate by an insulating layer. The data path cell includes an array of field-effect transistors wherein each transistor has, in the thin layer, a source region (S<SB>7</SB>), a drain region (D<SB>7</SB>), and a channel region (C<SB>7</SB>) bounded by the source and drain regions, and the data path cell further includes a front gate control region (GA<SB>7</SB>) formed above the channel region and is characterized in that at least one transistor (T<SB>7</SB>) has a back gate control region (GN<SB>2</SB>) formed in the bulk substrate beneath the channel region and a back gate region can be biased so as to modify the performance characteristics of the transistor. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011181896(A) 申请公布日期 2011.09.15
申请号 JP20100282122 申请日期 2010.12.17
申请人 SOITEC SILICON ON INSULATOR TECHNOLOGIES 发明人 MAZURE CARLOS;PHELAN RICHARD
分类号 H01L21/82;H01L21/822;H01L21/8234;H01L27/04;H01L27/08;H01L27/088;H01L29/786 主分类号 H01L21/82
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