发明名称 |
Method of manufacturing devices having vertical junction edge |
摘要 |
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties. |
申请公布号 |
US8084322(B2) |
申请公布日期 |
2011.12.27 |
申请号 |
US20060440260 |
申请日期 |
2006.05.24 |
申请人 |
GONZALEZ FERNANDO;MOULI CHANDRA;MICRON TECHNOLOGY, INC. |
发明人 |
GONZALEZ FERNANDO;MOULI CHANDRA |
分类号 |
H01L21/8242;H01L21/225;H01L21/336;H01L21/8234;H01L21/8238;H01L29/76;H01L29/78 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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