| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technology capable of improving the operating speed of a semiconductor device by reducing the resistance in an extension region on the source side of an FET formed on a semiconductor substrate. <P>SOLUTION: A first sidewall 6w and a second sidewall 6n having different widths in the gate length direction of a gate electrode 4d are formed, respectively, on the sidewall of the gate electrode 4d. Consequently, extension regions 37 and 38 are formed in self-alignment mannar under the first sidewall 6w and the second sidewall 6n with different widths on the upper surface of a semiconductor substrate SB. <P>COPYRIGHT: (C)2012,JPO&INPIT |
