| 摘要 |
Embodiments of methods and apparatus for optimization of verification of a chip design are disclosed. In various embodiments, a method for reducing a number of points to be verified during a verification process is disclosed, the method comprising selecting a first and a second verification point of a model of an integrated circuit design, determining whether the first and second verification points are isomorphic, and outputting the result of the determining to enable the first and second verification points being verified by verifying only a selected one of the first and second verification points in case the first and the second verification points are isomorphic. Additional variants and embodiments may also be disclosed and claimed. |
