发明名称 LEVEL CONVERTER
摘要 <P>PROBLEM TO BE SOLVED: To provide a level converter that decides an initial value of a latch circuit and implements satisfactory symmetry of rise/fall characteristics of an output signal. <P>SOLUTION: Initial value setting MOS transistors Tp3, Tp4 are inserted between nodes N1, N2 as output terminals and transistors Tp1, Tp2 of first and second inverter circuits 32, 33 constituting a latch circuit 31 of a shift circuit 12. A gate of the MOS transistor Tp3 is connected to a grounded, and a gate of the MOS transistor Tp4 is connected to an initial value setting circuit 34. The initial value setting circuit 34 controls the gate potential of the MOS transistor Tp4 at an intermediate potential between a second high potential power supply VDE and the ground when the second high potential power supply VDE is a predetermined level or lower, and controls the gate potential at the ground level to turn on the MOS transistor Tp4 when the second high potential power supply VDE is higher than the predetermined level. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012151896(A) 申请公布日期 2012.08.09
申请号 JP20120085270 申请日期 2012.04.04
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 KOTO TOMOHIKO
分类号 H03K19/0185 主分类号 H03K19/0185
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