发明名称 |
Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode |
摘要 |
Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.
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申请公布号 |
US8357573(B2) |
申请公布日期 |
2013.01.22 |
申请号 |
US20100772436 |
申请日期 |
2010.05.03 |
申请人 |
GLOBALFOUNDRIES, INC.;KRONHOLZ STEPHAN;LENSKI MARKUS;PAPAGEORGIOU VASSILIOS |
发明人 |
KRONHOLZ STEPHAN;LENSKI MARKUS;PAPAGEORGIOU VASSILIOS |
分类号 |
H01L21/8238;H01L21/336 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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