发明名称 PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES WITH IMPROVED TRANSFER FUNCTION
摘要 A connection scheme is used to selectively connect a dither capacitor included in a calibrated stage of a pipeline analog-to-digital converter (ADC) in a way that reduces the output voltage swing of the stage. A first terminal of the dither capacitor is coupled to an input of the amplifier. A second terminal of the dither capacitor is coupled to either a first or second reference voltage dependent on a bit value in a Pseudo-Random Binary Sequence (PRBS) if a voltage received by the stage is within a first voltage range. If the stage received voltage is within a second range, the second terminal is coupled to the first reference voltage independent of the PRBS. If the stage received voltage is within a third range, the second terminal is coupled to the second reference voltage independent of the PRBS.
申请公布号 US2013187802(A1) 申请公布日期 2013.07.25
申请号 US201313748430 申请日期 2013.01.23
申请人 SYNOPSYS, INC.;SYNOPSYS, INC. 发明人 DE FIGUEIREDO PEDRO MIGUEL FERREIRA
分类号 H03M1/10 主分类号 H03M1/10
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