发明名称 |
CACHE SET REPLACEMENT ORDER BASED ON TEMPORAL SET RECORDING |
摘要 |
A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.
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申请公布号 |
US2013191599(A1) |
申请公布日期 |
2013.07.25 |
申请号 |
US201213354894 |
申请日期 |
2012.01.20 |
申请人 |
BUSABA FADI Y.;CARLOUGH STEVEN R.;KRYGOWSKI CHRISTOPHER A.;PRASKY BRIAN R.;SHUM CHUNG-LUNG K.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUSABA FADI Y.;CARLOUGH STEVEN R.;KRYGOWSKI CHRISTOPHER A.;PRASKY BRIAN R.;SHUM CHUNG-LUNG K. |
分类号 |
G06F12/12 |
主分类号 |
G06F12/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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