SCAN TEST CIRCUIT, TEST PATTERN GENERATION CONTROL CIRCUIT, AND SCAN TEST CONTROL METHOD

摘要

To improve a delay fault coverage without increasing an area overhead, provided is a scan test circuit including: scan flip-flops forming a clock domain that operates according to the same clock within a semiconductor integrated circuit including a target of a delay fault test; a test pattern generation mode control unit (scan flip-flop) that is supplied with the same clock as that supplied to the scan flip-flops, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and a scan enable signal output unit (OR gate) that outputs a first scan enable signal, which is determined based on the test pattern generation mode, to the scan flip-flops.