| 摘要 |
A system (10) for managing a reference clock signal includes an XO (22), a signal buffer (24) coupled to the XO (22) and configured to drive a reference clock signal generated by the XO (22), and a first IC (12) coupled to the signal buffer (24). The first IC (12) includes an XO input buffer (32) configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit (34) configured to be in an enabled, operational state when the XO input buffer (32) is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism (36) configured to switch the XO input buffer (32) and the impedance equivalence circuit (34) between the enabled state and the disabled state. |
