发明名称 |
ARCHITECTURE FOR HIGH SPEED SERIAL TRANSMITTER |
摘要 |
PROBLEM TO BE SOLVED: To provide an architecture for a high speed serial transmitter.SOLUTION: A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce an input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer ("mux") as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference. |
申请公布号 |
JP2014027657(A) |
申请公布日期 |
2014.02.06 |
申请号 |
JP20130152362 |
申请日期 |
2013.07.23 |
申请人 |
ANALOG DEVICES INC |
发明人 |
AXEL ZAFRA-PETERSSON;MANSSON JOHAN HO;ELLIOTT MICHAEL R;JEFFRIES BRAD P |
分类号 |
H03K19/0175;H03K19/0948;H04L25/02;H04L25/03 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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