| 摘要 |
A semiconductor device includes a delay locked loop unit configured to compare a phase of an internal clock with a phase of a feedback clock to delay the internal clock by a delay amount corresponding to a comparison result, and to output a delay locked clock, a delay replica modeling unit configured to output the feedback clock by reflecting a transfer delay amount of the internal clock used in an internal circuit into the delay locked clock, and to adjust the transfer delay amount in response to a delay replica adjustment signal, and a delay replica adjustment signal generation unit configured to compare the phase of the feedback clock with a phase of the delay locked clock, and to set a value of the delay replica adjustment signal in response to a comparison result. |
