发明名称 3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof
摘要 A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
申请公布号 US8923050(B2) 申请公布日期 2014.12.30
申请号 US201313835032 申请日期 2013.03.15
申请人 SanDisk 3D LLC 发明人 Cernea Raul Adrian;Scheuerlein Roy E.
分类号 G11C11/34;G11C5/02;G11C5/06;H01L27/105;H01L21/768;G06F12/02;G11C7/18;G11C13/00;H01L27/24;H01L45/00 主分类号 G11C11/34
代理机构 Davis Wright Tremaine LLP 代理人 Davis Wright Tremaine LLP
主权项 1. A non-volatile memory, comprising: memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of parallel planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; a plurality of global bit lines elongated in the y-direction; and a vertical switch in line with each local bit line along the z-direction to switch one end of the local bit line to a corresponding global bit line, said vertical switch being a thin film transistor with a transistor junction in the z-direction in line with the local bit line and having a select gate, the select gate being insulated from said plurality of local bit lines and having a thickness extending along the x-direction between the local bit line and adjacent local bit lines on each side of the local bit line.
地址 Milpitas CA US