HEVC VIDEO ENCODER AND DECODER FOR MULTI-CORE

摘要

The disclosure provides a video encoder. The video encoder receives a frame and divides the frame into a plurality of tiles. The video encoder includes a plurality of video processing engines communicatively coupled with each other. Each video processing engine receives a tile of the plurality of tiles. A height of each tile is equal to a height of the frame and each tile comprises a plurality of rows. The plurality of video processing engines includes a first and a second video processing engine. The second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.

主权项

1. A video encoder configured to receive a frame and configured to divide the frame into a plurality of tiles, the video encoder comprising:
a plurality of video processing engines communicatively coupled with each other, each video processing engine configured to receive a tile of the plurality of tiles, wherein a height of each tile is equal to a height of the frame, and each tile comprises a plurality of rows; and a first and a second video processing engine of the plurality of video processing engines, the second video processing engine being initiated after the first video processing engines processes M rows of the plurality of rows of the tile, where M is an integer.