SEMICONDUCTOR DEVICE

摘要

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

主权项

1. A semiconductor device comprising:
a circuit to which an input signal is supplied; a first transistor; a second transistor; a first wiring to which a first potential is supplied, the first wiring electrically connected to a gate of the first transistor and a gate of the second transistor through the circuit; a second wiring to which a second potential is supplied, the second wiring electrically connected to one of a source and a drain of the first transistor; a third wiring to which a third potential is supplied, the third wiring electrically connected to the gate of the first transistor and the gate of the second transistor through the circuit; and a fourth wiring to which a first clock signal is supplied, the fourth wiring electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, wherein the circuit is configured to control electrical connections between the gates of the first and second transistors and the first and third wirings in accordance with the input signal and a second clock signal supplied to the circuit, wherein the first clock signal alternates the second potential and a fourth potential, and the second clock signal alternates the first potential and the third potential, wherein the second potential is higher than the first potential, wherein the third potential is higher than the second potential, wherein the fourth potential is equal to or higher than the third potential, and wherein the first transistor and the second transistor have the same conductivity type.